From 8c6fc0c15415b32080a848bbde640e104098cf13 Mon Sep 17 00:00:00 2001 From: Carlos Maiolino Date: Thu, 10 Jul 2025 22:18:39 +0200 Subject: Initial drop Add some riscv code Signed-off-by: Carlos Maiolino --- riscv/riscv-probe/env/qemu-sifive_e/default.lds | 47 +++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 riscv/riscv-probe/env/qemu-sifive_e/default.lds (limited to 'riscv/riscv-probe/env/qemu-sifive_e/default.lds') diff --git a/riscv/riscv-probe/env/qemu-sifive_e/default.lds b/riscv/riscv-probe/env/qemu-sifive_e/default.lds new file mode 100644 index 0000000..d27cc0c --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_e/default.lds @@ -0,0 +1,47 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 128M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >flash AT>flash :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >flash AT>flash :text + + .data : { + . = ALIGN(4096); + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} -- cgit v1.2.3