From 8c6fc0c15415b32080a848bbde640e104098cf13 Mon Sep 17 00:00:00 2001
From: Carlos Maiolino <cem@maiolino.dev>
Date: Thu, 10 Jul 2025 22:18:39 +0200
Subject: Initial drop

Add some riscv code

Signed-off-by: Carlos Maiolino <cem@toxiclabs.cc>
---
 riscv/riscv-probe/env/virt/crt.s       |  1 +
 riscv/riscv-probe/env/virt/default.lds | 46 ++++++++++++++++++++++++++++++++++
 riscv/riscv-probe/env/virt/setup.c     | 17 +++++++++++++
 3 files changed, 64 insertions(+)
 create mode 100644 riscv/riscv-probe/env/virt/crt.s
 create mode 100644 riscv/riscv-probe/env/virt/default.lds
 create mode 100644 riscv/riscv-probe/env/virt/setup.c

(limited to 'riscv/riscv-probe/env/virt')

diff --git a/riscv/riscv-probe/env/virt/crt.s b/riscv/riscv-probe/env/virt/crt.s
new file mode 100644
index 0000000..dcdf1e1
--- /dev/null
+++ b/riscv/riscv-probe/env/virt/crt.s
@@ -0,0 +1 @@
+.include "crtm.s"
diff --git a/riscv/riscv-probe/env/virt/default.lds b/riscv/riscv-probe/env/virt/default.lds
new file mode 100644
index 0000000..9c1a7df
--- /dev/null
+++ b/riscv/riscv-probe/env/virt/default.lds
@@ -0,0 +1,46 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  ram   (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M
+}
+
+PHDRS
+{
+  text PT_LOAD;
+  data PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  .text : {
+    PROVIDE(_text_start = .);
+    *(.text.init) *(.text .text.*)
+    PROVIDE(_text_end = .);
+  } >ram AT>ram :text
+
+  .rodata : {
+    PROVIDE(_rodata_start = .);
+    *(.rodata .rodata.*)
+    PROVIDE(_rodata_end = .);
+  } >ram AT>ram :text
+
+  .data : {
+    . = ALIGN(4096);
+    PROVIDE(_data_start = .);
+    *(.sdata .sdata.*) *(.data .data.*)
+    PROVIDE(_data_end = .);
+  } >ram AT>ram :data
+
+  .bss :{
+    PROVIDE(_bss_start = .);
+    *(.sbss .sbss.*) *(.bss .bss.*)
+    PROVIDE(_bss_end = .);
+  } >ram AT>ram :bss
+
+  PROVIDE(_memory_start = ORIGIN(ram));
+  PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram));
+}
diff --git a/riscv/riscv-probe/env/virt/setup.c b/riscv/riscv-probe/env/virt/setup.c
new file mode 100644
index 0000000..dcd87a3
--- /dev/null
+++ b/riscv/riscv-probe/env/virt/setup.c
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+#include "femto.h"
+
+auxval_t __auxv[] = {
+    { UART0_CLOCK_FREQ,         1843200    },
+    { UART0_BAUD_RATE,          115200     },
+    { NS16550A_UART0_CTRL_ADDR, 0x10000000 },
+    { SIFIVE_TEST_CTRL_ADDR,    0x100000   },
+    { 0, 0 }
+};
+
+void arch_setup()
+{
+    register_console(&console_ns16550a);
+    register_poweroff(&poweroff_sifive_test);
+}
-- 
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