From 8c6fc0c15415b32080a848bbde640e104098cf13 Mon Sep 17 00:00:00 2001 From: Carlos Maiolino Date: Thu, 10 Jul 2025 22:18:39 +0200 Subject: Initial drop Add some riscv code Signed-off-by: Carlos Maiolino --- riscv/sections/sections.rv | Bin 0 -> 992 bytes riscv/sections/sections.s | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100755 riscv/sections/sections.rv create mode 100644 riscv/sections/sections.s (limited to 'riscv/sections') diff --git a/riscv/sections/sections.rv b/riscv/sections/sections.rv new file mode 100755 index 0000000..9b96da0 Binary files /dev/null and b/riscv/sections/sections.rv differ diff --git a/riscv/sections/sections.s b/riscv/sections/sections.s new file mode 100644 index 0000000..8e83ec1 --- /dev/null +++ b/riscv/sections/sections.s @@ -0,0 +1,23 @@ +# Messing up with ASM sections + +.section .data + x: .word 10 + +.section .text + update_x: + la t1, x + sw a0, (t1) + ret + +# We can mix sections in different parts of the source +# The assembler will take care of merging them together in +# the object file + +.section .data + y: .word 99 + +.section .text + update_y: + la t1, y + sw a0, (t1) + ret -- cgit v1.2.3