diff options
| author | Carlos Maiolino <[email protected]> | 2025-07-10 22:18:39 +0200 |
|---|---|---|
| committer | Carlos Maiolino <[email protected]> | 2025-07-10 22:18:39 +0200 |
| commit | 8c6fc0c15415b32080a848bbde640e104098cf13 (patch) | |
| tree | 04a21bd28f9dc82c8e216390d6208ed93b9bcd11 /riscv/riscv-probe/env/spike | |
Initial drop
Add some riscv code
Signed-off-by: Carlos Maiolino <[email protected]>
Diffstat (limited to 'riscv/riscv-probe/env/spike')
| -rw-r--r-- | riscv/riscv-probe/env/spike/crt.s | 1 | ||||
| -rw-r--r-- | riscv/riscv-probe/env/spike/default.lds | 52 | ||||
| -rw-r--r-- | riscv/riscv-probe/env/spike/setup.c | 18 |
3 files changed, 71 insertions, 0 deletions
diff --git a/riscv/riscv-probe/env/spike/crt.s b/riscv/riscv-probe/env/spike/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/spike/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/spike/default.lds b/riscv/riscv-probe/env/spike/default.lds new file mode 100644 index 0000000..eb78711 --- /dev/null +++ b/riscv/riscv-probe/env/spike/default.lds @@ -0,0 +1,52 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; + htif PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >ram AT>ram :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >ram AT>ram :text + + .htif : { + . = ALIGN(4096); + *(.htif) + } >ram AT>ram :text + + .data : { + . = ALIGN(4096); + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/spike/setup.c b/riscv/riscv-probe/env/spike/setup.c new file mode 100644 index 0000000..54d4bf1 --- /dev/null +++ b/riscv/riscv-probe/env/spike/setup.c @@ -0,0 +1,18 @@ +// See LICENSE for license details. + +#include "femto.h" + +extern uint64_t tohost; +extern uint64_t fromhost; + +auxval_t __auxv[] = { + { RISCV_HTIF_BASE_ADDR, 0 }, + { 0, 0 } +}; + +void arch_setup() +{ + __auxv[0].val = (uintptr_t)(&tohost < &fromhost ? &tohost : &fromhost); + register_console(&console_htif); + register_poweroff(&poweroff_htif); +} |
