diff options
| author | Carlos Maiolino <[email protected]> | 2025-07-10 22:18:39 +0200 |
|---|---|---|
| committer | Carlos Maiolino <[email protected]> | 2025-07-10 22:18:39 +0200 |
| commit | 8c6fc0c15415b32080a848bbde640e104098cf13 (patch) | |
| tree | 04a21bd28f9dc82c8e216390d6208ed93b9bcd11 /riscv/riscv-probe/libfemto/include/auxval.h | |
Initial drop
Add some riscv code
Signed-off-by: Carlos Maiolino <[email protected]>
Diffstat (limited to 'riscv/riscv-probe/libfemto/include/auxval.h')
| -rw-r--r-- | riscv/riscv-probe/libfemto/include/auxval.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/riscv/riscv-probe/libfemto/include/auxval.h b/riscv/riscv-probe/libfemto/include/auxval.h new file mode 100644 index 0000000..de10824 --- /dev/null +++ b/riscv/riscv-probe/libfemto/include/auxval.h @@ -0,0 +1,34 @@ +// See LICENSE for license details. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + HART0_CLOCK_FREQ = 0x00010000, + UART0_CLOCK_FREQ = 0x00011000, + UART0_BAUD_RATE = 0x00011100, + NS16550A_UART0_CTRL_ADDR = 0x00030000, + RISCV_HTIF_BASE_ADDR = 0x00050000, + SIFIVE_CLINT_CTRL_ADDR = 0x55550000, + SIFIVE_CLIC_CRTL_ADDR = 0x55550001, + SIFIVE_TEST_CTRL_ADDR = 0x55550002, + SIFIVE_UART0_CTRL_ADDR = 0x55550010, + SIFIVE_GPIO0_CTRL_ADDR = 0x55550020, + SIFIVE_SPI0_CTRL_ADDR = 0x55550030, +}; + +typedef struct auxval { + unsigned long key; + unsigned long val; +} auxval_t; + +extern auxval_t __auxv[]; + +unsigned long getauxval(unsigned long key); + +#ifdef __cplusplus +} +#endif |