summaryrefslogtreecommitdiff
path: root/riscv/sections/sections.s
diff options
context:
space:
mode:
authorCarlos Maiolino <[email protected]>2025-07-10 22:18:39 +0200
committerCarlos Maiolino <[email protected]>2025-07-10 22:18:39 +0200
commit8c6fc0c15415b32080a848bbde640e104098cf13 (patch)
tree04a21bd28f9dc82c8e216390d6208ed93b9bcd11 /riscv/sections/sections.s
Initial drop
Add some riscv code Signed-off-by: Carlos Maiolino <[email protected]>
Diffstat (limited to 'riscv/sections/sections.s')
-rw-r--r--riscv/sections/sections.s23
1 files changed, 23 insertions, 0 deletions
diff --git a/riscv/sections/sections.s b/riscv/sections/sections.s
new file mode 100644
index 0000000..8e83ec1
--- /dev/null
+++ b/riscv/sections/sections.s
@@ -0,0 +1,23 @@
+# Messing up with ASM sections
+
+.section .data
+ x: .word 10
+
+.section .text
+ update_x:
+ la t1, x
+ sw a0, (t1)
+ ret
+
+# We can mix sections in different parts of the source
+# The assembler will take care of merging them together in
+# the object file
+
+.section .data
+ y: .word 99
+
+.section .text
+ update_y:
+ la t1, y
+ sw a0, (t1)
+ ret