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authorCarlos Maiolino <[email protected]>2025-07-10 22:55:07 +0200
committerCarlos Maiolino <[email protected]>2025-07-10 22:56:55 +0200
commitd98f46ce647846b0aa30b2e16a30fd4e152a1bf5 (patch)
tree267474fcc77cf20b428f6f4c7f768ca09f4cfe0e /msp340/Timers/main.c
parent869e68986aa8f69af6e7842260a68d1e5c6f796f (diff)
Add new code
Signed-off-by: Carlos Maiolino <[email protected]>
Diffstat (limited to 'msp340/Timers/main.c')
-rwxr-xr-xmsp340/Timers/main.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/msp340/Timers/main.c b/msp340/Timers/main.c
new file mode 100755
index 0000000..59ecbdd
--- /dev/null
+++ b/msp340/Timers/main.c
@@ -0,0 +1,35 @@
+#include <msp430.h>
+
+#define UP 0x0010 // Set MC bits to enable TimerA UP mode
+#define ACLK 0x0100 // Configure TimerA to use the aux clock
+
+#define TIME_LIMIT 5000 // Timer limit
+
+#define RED_LED 0x0001
+#define WDT_OFF 0x5A80
+#define ENABLE_PINS 0xFFFE
+
+#define TA_INT_FLAG 0x0001 // TimerA_0 CTL Register bit interrupt flag
+ // Raised by the timer when it reached its count
+
+main() {
+ WDTCTL = WDT_OFF; // Disable watchdog
+ PM5CTL0 = ENABLE_PINS; // Enable I/O pins
+
+ TA0CCR0 = TIME_LIMIT; // Set Capture/Compare Register to the number we want the
+ // timer to count. The timer compares its count with the number stored here.
+ TA0CTL = ACLK | UP; // Setup TimerA_0 to UP mode
+
+
+ P1DIR = RED_LED; // Set P1.0 pin as output
+
+ while (1) {
+
+ if (TA0CTL & TA_INT_FLAG) {
+ P1OUT ^= RED_LED;
+
+ // Reset timer by disabling its interrupt flag
+ TA0CTL &= ~TA_INT_FLAG;
+ }
+ }
+}