1 files changed, 17 insertions, 0 deletions
diff --git a/riscv/riscv-probe/env/qemu-sifive_u/setup.c b/riscv/riscv-probe/env/qemu-sifive_u/setup.c
new file mode 100644
index 0000000..840e778
--- /dev/null
+++ b/riscv/riscv-probe/env/qemu-sifive_u/setup.c
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+#include "femto.h"
+
+auxval_t __auxv[] = {
+    { UART0_CLOCK_FREQ,         32000000   },
+    { UART0_BAUD_RATE,          115200     },
+    { SIFIVE_UART0_CTRL_ADDR,   0x10013000 },
+    { SIFIVE_TEST_CTRL_ADDR,    0x100000   },
+    { 0, 0 }
+};
+
+void arch_setup()
+{
+    register_console(&console_sifive_uart);
+    register_poweroff(&poweroff_sifive_test);
+}