diff options
Diffstat (limited to 'riscv/riscv-probe/env')
25 files changed, 624 insertions, 0 deletions
diff --git a/riscv/riscv-probe/env/common/constants.s b/riscv/riscv-probe/env/common/constants.s new file mode 100644 index 0000000..d08387c --- /dev/null +++ b/riscv/riscv-probe/env/common/constants.s @@ -0,0 +1,18 @@ +# See LICENSE for license details. + +.equ MAX_HARTS, 4 +.equ SAVE_REGS, 16 +.equ STACK_SIZE, 1024 +.equ STACK_SHIFT, 10 +.equ CONTEXT_SIZE, (SAVE_REGS * REGBYTES) + +.globl _text_start +.globl _text_end +.globl _rodata_start +.globl _rodata_end +.globl _data_start +.globl _data_end +.globl _bss_start +.globl _bss_end +.global _memory_start; +.global _memory_end; diff --git a/riscv/riscv-probe/env/common/crtm.s b/riscv/riscv-probe/env/common/crtm.s new file mode 100644 index 0000000..9dc84b2 --- /dev/null +++ b/riscv/riscv-probe/env/common/crtm.s @@ -0,0 +1,89 @@ +# See LICENSE for license details. + +.include "macros.s" +.include "constants.s" + +# +# start of trap handler +# + +.section .text.init,"ax",@progbits +.globl _start + +_start: + # setup default trap vector + la t0, trap_vector + csrw mtvec, t0 + + # set up stack pointer based on hartid + csrr t0, mhartid + slli t0, t0, STACK_SHIFT + la sp, stacks + STACK_SIZE + add sp, sp, t0 + + # park all harts excpet hart 0 + csrr a0, mhartid + bnez a0, park + + # jump to libfemto_start_main + j libfemto_start_main + + # sleeping harts mtvec calls trap_fn upon receiving IPI +park: + wfi + j park + + .align 2 +trap_vector: + # Save registers. + addi sp, sp, -CONTEXT_SIZE + sxsp ra, 0 + sxsp a0, 1 + sxsp a1, 2 + sxsp a2, 3 + sxsp a3, 4 + sxsp a4, 5 + sxsp a5, 6 + sxsp a6, 7 + sxsp a7, 8 + sxsp t0, 9 + sxsp t1, 10 + sxsp t2, 11 + sxsp t3, 12 + sxsp t4, 13 + sxsp t5, 14 + sxsp t6, 15 + + # Invoke the handler. + mv a0, sp + csrr a1, mcause + csrr a2, mepc + jal trap_handler + + # Restore registers. + lxsp ra, 0 + lxsp a0, 1 + lxsp a1, 2 + lxsp a2, 3 + lxsp a3, 4 + lxsp a4, 5 + lxsp a5, 6 + lxsp a6, 7 + lxsp a7, 8 + lxsp t0, 9 + lxsp t1, 10 + lxsp t2, 11 + lxsp t3, 12 + lxsp t4, 13 + lxsp t5, 14 + lxsp t6, 15 + addi sp, sp, CONTEXT_SIZE + + # Return + mret + + .bss + .align 4 + .global stacks +stacks: + .skip STACK_SIZE * MAX_HARTS diff --git a/riscv/riscv-probe/env/common/rv32/macros.s b/riscv/riscv-probe/env/common/rv32/macros.s new file mode 100644 index 0000000..d987d0c --- /dev/null +++ b/riscv/riscv-probe/env/common/rv32/macros.s @@ -0,0 +1,23 @@ +# See LICENSE for license details. + +.equ REGBYTES, 4 + +.macro lx a, b +lw \a, \b +.endm + +.macro sx a, b +sw \a, \b +.endm + +.macro lxsp a, b +lw \a, ((\b)*REGBYTES)(sp) +.endm + +.macro sxsp a, b +sw \a, ((\b)*REGBYTES)(sp) +.endm + +.macro .ptr a +.4byte \a +.endm diff --git a/riscv/riscv-probe/env/common/rv64/macros.s b/riscv/riscv-probe/env/common/rv64/macros.s new file mode 100644 index 0000000..abc76f0 --- /dev/null +++ b/riscv/riscv-probe/env/common/rv64/macros.s @@ -0,0 +1,23 @@ +# See LICENSE for license details. + +.equ REGBYTES, 8 + +.macro lx a, b +ld \a, \b +.endm + +.macro sx a, b +sd \a, \b +.endm + +.macro lxsp a, b +ld \a, ((\b)*REGBYTES)(sp) +.endm + +.macro sxsp a, b +sd \a, ((\b)*REGBYTES)(sp) +.endm + +.macro .ptr a +.8byte \a +.endm diff --git a/riscv/riscv-probe/env/coreip-e2-arty/crt.s b/riscv/riscv-probe/env/coreip-e2-arty/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/coreip-e2-arty/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/coreip-e2-arty/default.lds b/riscv/riscv-probe/env/coreip-e2-arty/default.lds new file mode 100644 index 0000000..b7aa9b2 --- /dev/null +++ b/riscv/riscv-probe/env/coreip-e2-arty/default.lds @@ -0,0 +1,46 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 128M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >flash AT>flash :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >flash AT>flash :text + + .data : { + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/coreip-e2-arty/setup.c b/riscv/riscv-probe/env/coreip-e2-arty/setup.c new file mode 100644 index 0000000..9dbecba --- /dev/null +++ b/riscv/riscv-probe/env/coreip-e2-arty/setup.c @@ -0,0 +1,20 @@ +// See LICENSE for license details. + +#include "femto.h" + +auxval_t __auxv[] = { + { UART0_CLOCK_FREQ, 32000000 }, + { UART0_BAUD_RATE, 115200 }, + { SIFIVE_UART0_CTRL_ADDR, 0x20000000 }, + { 0, 0 } +}; + +void arch_setup() +{ + /* + * clock setup code should be placed here and should modify the + * uart clock speed before calling register_console, which calls + * uart_init and reads the uart clock speed from the config array. + */ + register_console(&console_sifive_uart); +} diff --git a/riscv/riscv-probe/env/default/crt.s b/riscv/riscv-probe/env/default/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/default/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/default/default.lds b/riscv/riscv-probe/env/default/default.lds new file mode 100644 index 0000000..c103c78 --- /dev/null +++ b/riscv/riscv-probe/env/default/default.lds @@ -0,0 +1,45 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >ram AT>ram :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >ram AT>ram :text + + .data : { + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/default/setup.c b/riscv/riscv-probe/env/default/setup.c new file mode 100644 index 0000000..47674ca --- /dev/null +++ b/riscv/riscv-probe/env/default/setup.c @@ -0,0 +1,9 @@ +// See LICENSE for license details. + +#include "femto.h" + +auxval_t __auxv[] = { + { 0, 0 } +}; + +void arch_setup() {} diff --git a/riscv/riscv-probe/env/qemu-sifive_e/crt.s b/riscv/riscv-probe/env/qemu-sifive_e/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_e/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/qemu-sifive_e/default.lds b/riscv/riscv-probe/env/qemu-sifive_e/default.lds new file mode 100644 index 0000000..d27cc0c --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_e/default.lds @@ -0,0 +1,47 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 128M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >flash AT>flash :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >flash AT>flash :text + + .data : { + . = ALIGN(4096); + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/qemu-sifive_e/setup.c b/riscv/riscv-probe/env/qemu-sifive_e/setup.c new file mode 100644 index 0000000..840e778 --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_e/setup.c @@ -0,0 +1,17 @@ +// See LICENSE for license details. + +#include "femto.h" + +auxval_t __auxv[] = { + { UART0_CLOCK_FREQ, 32000000 }, + { UART0_BAUD_RATE, 115200 }, + { SIFIVE_UART0_CTRL_ADDR, 0x10013000 }, + { SIFIVE_TEST_CTRL_ADDR, 0x100000 }, + { 0, 0 } +}; + +void arch_setup() +{ + register_console(&console_sifive_uart); + register_poweroff(&poweroff_sifive_test); +} diff --git a/riscv/riscv-probe/env/qemu-sifive_u/crt.s b/riscv/riscv-probe/env/qemu-sifive_u/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_u/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/qemu-sifive_u/default.lds b/riscv/riscv-probe/env/qemu-sifive_u/default.lds new file mode 100644 index 0000000..9c1a7df --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_u/default.lds @@ -0,0 +1,46 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >ram AT>ram :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >ram AT>ram :text + + .data : { + . = ALIGN(4096); + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/qemu-sifive_u/setup.c b/riscv/riscv-probe/env/qemu-sifive_u/setup.c new file mode 100644 index 0000000..840e778 --- /dev/null +++ b/riscv/riscv-probe/env/qemu-sifive_u/setup.c @@ -0,0 +1,17 @@ +// See LICENSE for license details. + +#include "femto.h" + +auxval_t __auxv[] = { + { UART0_CLOCK_FREQ, 32000000 }, + { UART0_BAUD_RATE, 115200 }, + { SIFIVE_UART0_CTRL_ADDR, 0x10013000 }, + { SIFIVE_TEST_CTRL_ADDR, 0x100000 }, + { 0, 0 } +}; + +void arch_setup() +{ + register_console(&console_sifive_uart); + register_poweroff(&poweroff_sifive_test); +} diff --git a/riscv/riscv-probe/env/semihost/crt.s b/riscv/riscv-probe/env/semihost/crt.s new file mode 100644 index 0000000..b75cba8 --- /dev/null +++ b/riscv/riscv-probe/env/semihost/crt.s @@ -0,0 +1,28 @@ +# See LICENSE for license details. + +.include "macros.s" +.include "constants.s" + +# +# start of trap handler +# + +.section .text.init,"ax",@progbits +.globl _start + +_start: + + # set up stack pointer based on hartid (in a0) + mv t0, a0 + slli t0, t0, STACK_SHIFT + la sp, stacks + STACK_SIZE + add sp, sp, t0 + + # jump to libfemto_start_main + j libfemto_start_main + + .bss + .align 4 + .global stacks +stacks: + .skip STACK_SIZE * MAX_HARTS diff --git a/riscv/riscv-probe/env/semihost/default.lds b/riscv/riscv-probe/env/semihost/default.lds new file mode 100644 index 0000000..c103c78 --- /dev/null +++ b/riscv/riscv-probe/env/semihost/default.lds @@ -0,0 +1,45 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >ram AT>ram :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >ram AT>ram :text + + .data : { + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/semihost/setup.c b/riscv/riscv-probe/env/semihost/setup.c new file mode 100644 index 0000000..407ee14 --- /dev/null +++ b/riscv/riscv-probe/env/semihost/setup.c @@ -0,0 +1,12 @@ +// See LICENSE for license details. + +#include "femto.h" + +auxval_t __auxv[] = { + { 0, 0 } +}; + +void arch_setup() { + register_console(&console_semihost); + register_poweroff(&poweroff_semihost); +} diff --git a/riscv/riscv-probe/env/spike/crt.s b/riscv/riscv-probe/env/spike/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/spike/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/spike/default.lds b/riscv/riscv-probe/env/spike/default.lds new file mode 100644 index 0000000..eb78711 --- /dev/null +++ b/riscv/riscv-probe/env/spike/default.lds @@ -0,0 +1,52 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; + htif PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >ram AT>ram :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >ram AT>ram :text + + .htif : { + . = ALIGN(4096); + *(.htif) + } >ram AT>ram :text + + .data : { + . = ALIGN(4096); + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/spike/setup.c b/riscv/riscv-probe/env/spike/setup.c new file mode 100644 index 0000000..54d4bf1 --- /dev/null +++ b/riscv/riscv-probe/env/spike/setup.c @@ -0,0 +1,18 @@ +// See LICENSE for license details. + +#include "femto.h" + +extern uint64_t tohost; +extern uint64_t fromhost; + +auxval_t __auxv[] = { + { RISCV_HTIF_BASE_ADDR, 0 }, + { 0, 0 } +}; + +void arch_setup() +{ + __auxv[0].val = (uintptr_t)(&tohost < &fromhost ? &tohost : &fromhost); + register_console(&console_htif); + register_poweroff(&poweroff_htif); +} diff --git a/riscv/riscv-probe/env/virt/crt.s b/riscv/riscv-probe/env/virt/crt.s new file mode 100644 index 0000000..dcdf1e1 --- /dev/null +++ b/riscv/riscv-probe/env/virt/crt.s @@ -0,0 +1 @@ +.include "crtm.s" diff --git a/riscv/riscv-probe/env/virt/default.lds b/riscv/riscv-probe/env/virt/default.lds new file mode 100644 index 0000000..9c1a7df --- /dev/null +++ b/riscv/riscv-probe/env/virt/default.lds @@ -0,0 +1,46 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + text PT_LOAD; + data PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + .text : { + PROVIDE(_text_start = .); + *(.text.init) *(.text .text.*) + PROVIDE(_text_end = .); + } >ram AT>ram :text + + .rodata : { + PROVIDE(_rodata_start = .); + *(.rodata .rodata.*) + PROVIDE(_rodata_end = .); + } >ram AT>ram :text + + .data : { + . = ALIGN(4096); + PROVIDE(_data_start = .); + *(.sdata .sdata.*) *(.data .data.*) + PROVIDE(_data_end = .); + } >ram AT>ram :data + + .bss :{ + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) *(.bss .bss.*) + PROVIDE(_bss_end = .); + } >ram AT>ram :bss + + PROVIDE(_memory_start = ORIGIN(ram)); + PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram)); +} diff --git a/riscv/riscv-probe/env/virt/setup.c b/riscv/riscv-probe/env/virt/setup.c new file mode 100644 index 0000000..dcd87a3 --- /dev/null +++ b/riscv/riscv-probe/env/virt/setup.c @@ -0,0 +1,17 @@ +// See LICENSE for license details. + +#include "femto.h" + +auxval_t __auxv[] = { + { UART0_CLOCK_FREQ, 1843200 }, + { UART0_BAUD_RATE, 115200 }, + { NS16550A_UART0_CTRL_ADDR, 0x10000000 }, + { SIFIVE_TEST_CTRL_ADDR, 0x100000 }, + { 0, 0 } +}; + +void arch_setup() +{ + register_console(&console_ns16550a); + register_poweroff(&poweroff_sifive_test); +} |